Apr. 20th - Janice McMahon, Engineer at EMU Technologies


April 20th, 2:00 p.m. at the University of Virginia, Monroe #130

Janice McMahon is a lead engineer at EMU Technology, a company that is revolutionizing the way we think about data science problems with entirely new computer architectures.

Migratory Thread and Memory-Side Processing

The need for a new computing architecture arises when we hit a technology wall for important classes of applications. In contrast with the Memory Wall of the mid-90s and the Power Wall of the mid-2000s, today’s wall is largely due to the emergence of applications with memory-intensive characteristics. The lack of Locality in these applications means that today’s architectures will not break through the wall with technological advances alone, and a shift in computing paradigm is required.

The Emu Technology team’s approach to addressing the needs of today’s High-Performance Data Analytics applications involves two key steps: firstly, place computational resources physically near the memory units in the architecture to ameliorate memory bandwidth concerns; and secondly, move processing state during a computation to mitigate the loss of efficiency that results from excessive messaging in an application. We call this new paradigm Migratory Memory-Side Processing (MMSP), and the result is a system specifically designed to make it possible to solve graph analytics and sparse matrices efficiently, using less energy than conventional computers. Instead of moving massive amounts of data to CPUs or GPUs like conventional computers, the Emu system utilizes thousands of threads which run on Emu-developed lightweight cores which are spread out throughout system memory. MMSP migrates the instructions to perform a calculation to the data location in memory, requiring far fewer system resources than moving data to a CPU. For applications like graph analytics, non-linear partial differential equations with stochastic methods, sparse matrix mathematics, Jaccard similarity, and breadth first search for graph analytics, MMSP performs computations on non-zero elements without requiring movement of large blocks of data containing the zero elements that are not utilized in the computation. This improvement in processing efficiency is achieved via a programming model that is familiar to developers and easy to use, unlike other novel architectures that require extensive programmer re-training. The result is a computer that can be used to solve mathematical problems even the largest clusters cannot handle.

In this talk, the Emu computing paradigm and its motivation will be presented at a high level, with enough detail on the architecture and programming model to convey the basic features of the system, their practical use, and the resulting advantages to modern applications. Presentations that provide much more depth on the detailed features of the system will be available upon request and can be brought forth during the Q&A, if desired.

About Janice McMahon

Janice McMahon has an extensive background in massively parallel computation, advanced computing architectures, algorithm and application mapping, and signal and image processing embedded computing. After attaining B.S. and M.S. degrees in Computer Science and Engineering from M.I.T., Ms. McMahon has worked in research, industry, and government environments within the high-performance computing industry. Within the research community, she has worked at MIT Lincoln Laboratory, Information Sciences Institute, and Reservoir Labs on advanced algorithms and architectures for a variety of high performance applications, as both researcher and project manager. Within the computing industry, she has worked on state-of-the-art software and hardware architectures at MasPar Computer Corporation, Scientific Computing and Analysis, HPC Project (now Sylvan), and currently, Emu Technology. Within the government, defense industry, she has worked on radar and sonar applications at G.T.E., Raytheon, and Analysis & Technology Corporation. Throughout her 30-year career, she has been exposed to a large variety of advanced research and commercial computer architectures as well as a broad range of high performance applications and algorithms. Her technical specialties include parallel algorithm mapping and performance analysis.

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